Copper Interconnect Technology by Tapan Gupta

By Tapan Gupta

Since total circuit functionality has depended totally on transistor houses, past efforts to augment circuit and process pace have been considering transistors in addition. over the past decade, in spite of the fact that, the parasitic resistance, capacitance, and inductance linked to interconnections started to effect circuit functionality and should be the first elements within the evolution of nanoscale ULSI expertise. simply because metal conductivity and resistance to electromigration of bulk copper (Cu) are higher than aluminum, use of copper and low-k fabrics now prevails within the foreign microelectronics undefined. even if, because the characteristic dimension of the Cu-lines forming interconnects is scaled, resistivity of the traces raises. even as electromigration and stress-induced voids as a result of elevated present density develop into major reliability concerns. even if copper/low-k expertise has develop into relatively mature, there is not any unmarried booklet to be had at the promise and demanding situations of those next-generation applied sciences. during this publication, a pacesetter within the box describes complex laser structures with reduce radiation wavelengths, photolithography fabrics, and mathematical modeling ways to handle the demanding situations of Cu-interconnect know-how.

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But the process seems to be challenging for the future IC industry. At the same time continued reduction of gate length demands a new high-K dielectric material which will be able to suppress the tunneling current while maintaining the drain current necessary for low standby power (LSTP). Thus for gate electrode, we need a new material and deposition process as oxynitride films have reached onan unacceptable level. On the other hand, in 65 nm node technology the basic transistor architecture will mainly be associated with processing and integration of the gate stack with a highly doped ultra-shallow junction (USJ) contacting the device.

The technology is known as the damascene process. 28 shows a schematic of a Cu-damascene architecture. Barrier layer Seed layer Electroplated copper Fig. 28 The conventional Cu-damascene architecture 24 1 Introduction Copper is deposited by an electrochemical method over a Cu-seed layer. The Cu-film grows along the <111> direction with smaller grains but with time the grains grow larger even at room temperature. Studies have shown that electromigration (EM) performance, measured by the median time to failure (MTTF) can be improved by controlling the texture of the Cu-film.

11 μm2 (Reprinted with permission, Semiconductor International, Oct. 2003, p. 28) 38 1 Introduction The miniaturization of devices for high-speed circuits went on unabated, and by the end of 2003, a functional static random access memory (SRAM) chip was fabricated following 90 nm node technology. 57 um2 cell size was fabricated by adopting the 65 nm process (Fig. 47). 13 Technologies of the 21st Century, and the Plan to Meet the Challenges The last two centuries have seen an increasing flood of inventions and discoveries.

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