CMOS Integrated Switching Power Converters: A Structured by Gerard Villar Piqué

By Gerard Villar Piqué

This publication describes the established layout and optimization of effective, power processing built-in circuits. The technique is multidisciplinary, masking the monolithic integration of IC layout thoughts, energy electronics and keep watch over concept. particularly, this e-book permits readers to conceive, synthesize, layout and enforce built-in circuits with high-density high-efficiency on-chip switching energy regulators. subject matters lined surround the based layout of the on-chip energy provide, potency optimization, IC-compatible energy inductors and capacitors, energy MOSFET switches and effective swap drivers in general CMOS applied sciences.

  • Provides a accomplished reference on based layout and optimization of totally monolithic energy provides for on-chip strength administration;
  • Describes a multidisciplinary procedure, encompassing more advantageous built-in energy units, either energetic and reactive, in addition to complex circuit topologies and switching keep watch over equipment, including their implementation;
  • Enables concurrent layout of compact adaptive strength provides, including system-level and circuit-level techniques.

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Extra resources for CMOS Integrated Switching Power Converters: A Structured Design Approach

Example text

Output capacitor optimized design characteristics . . . . . . . . . . Buck converter power switches optimized design characteristics . . . Compared converters main parameters . . . . . . . . . . . . . . v A and v B values along the four different converter states (large C x capacitor is considered) . . . . . . . . . . . . . . . . . . . . Switching sequence for any of the transistors of a DCM operated 3-level Buck converter (0 stands for ‘off-state’, whereas 1 stands for ‘on-state’) .

166 166 167 168 174 189 191 191 191 192 193 193 242 Table of Symbols Symbol ACc ACo ACr AL AMOS Adriver Atotal B C CA CB CMIM C PAD CT C Vx C dd C gate C in C jd C mm Cn Co C out C ox C poly−poly C sd C sg Cx D1 D3 Meaning MOSCAP structure capacitive area Output capacitor occupied area MOSCAP structure routing area Inductor occupied area Power MOS occupied area Driver occupied area Total occupied area Magnetic flux density Integration capacitor in the dnN1 and dnN2 signals generation circuits (Sect.

Complete set of characteristics of the optimized design after the application of the output ripple constraint . . . . . . . . . . . . . Main characteristics and parameters of the optimized inductor design . Technological values used in example MOSCAP calculations . . . . Parameters used to characterize the tapered buffer . . . . . . . . . Voltage excursions in the switching nodes of a DCM operated buck converter, and instantaneous transistor current value for each state change .

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